Current complementary metal-oxide-semiconductor (CMOS) devices typically use metal gate materials to control transistor threshold voltage through the effective work function of a multi-layer metal stack. Different threshold voltages in a selected CMOS device may be achieved by changing the material and/or layer thickness of the metal gate stack to achieve the selected threshold voltage in each device. The current method of achieving multiple threshold voltages is a hybrid of selective well and halo implants and spatial control of the metal gate stack. While photo-patterning of well and halo implants is effective, continued fin width reduction is reducing the effectiveness of the well and halo implants, while the process remains intrinsically variable due to random dopant fluctuations. Spatial control of a metal gate stack can be achieved through a combination of photopatterning and etching in order to differentiate between n-type metal oxide semiconductor (NMOS) devices and p-type metal oxide semiconductor (PMOS) devices. However, the selective etching of the spatial control process uses an added etch stop layer, which consumes critical space in short gate length devices. Furthermore, the higher aspect ratio metal gate structures for future CMOS devices will utilize very high selectivity for removal of unwanted metal gate layers, which may render current methods impractical.
Accordingly, the inventors have developed improved methods of forming semiconductor devices.